The present invention relates to integrated circuits, particularly to integrated circuits manufactured using silicon-on-sapphire (SOS) technology.
A problem has heretofore existed in controlling the leakage of the N-channel (NMOS) transistor in complementary symmetry metal oxide semiconductor (CMOS) SOS integrated circuits or in NMOS/SOS integrated circuits when the threshold voltage of the NMOS transistor is very low. The reason for the problem's existence is that every open geometry, i.e. non C.sup.2 L, transistor manufactured using SOS technology really consists of three transistors in parallel. The three transistors are a top transistor manufactured on the flat upper surface of the silicon island, i.e. on a silicon surface which is parallel to the (100) crystallographic plane and a pair of "edge transistors" which are manufactured on the edge of the island, i.e. on a silicon surface parallel to the (111) crystallographic plane. Since the edge transistors on the (111) silicon have a threshold voltage approximately 0.7 volts to 1.0 volt lower than the top transistor, there is normally no problem when the integrated circuit is operated from a standard power supply voltage in the range of from 5 to 10 volts. The reason that there is normally no problem is that the top N-channel transistor threshold is generally set to be at least 1.5 volts, so the edge transistors are turned off when the top transistor is turned off. However, there will be a problem if the threshold voltage of the top transistor is reduced to below about 1.0 volt for low voltage operation. There will also be a problem if the N-channel transistors' thresholds shift due to radiation exposure. Then, the associated shift in the threshold voltage of (111) edge transistors is even greater than that of the top transistor, and the shift can cause the edge transistors to go well into the depletion range. The shift in threshold voltage of the edge transistors is a major cause of post-radiation leakage current in SOS arrays.
In order to avoid the problems set forth above, the edge transistor leakage could be controlled by providing a guardband, i.e. a heavily doped region, around the edge of the island in order to raise the threshold voltage of the edge transistors by increasing their surface impurity concentrations. This has generally not been done in the past, because no way of doing it which would not consume extra area and involve an additional photomask step was known heretofore.
Heretofore various approaches have been utilized in manufacturing low leakage NMOS/SOS transistors. Such approaches are described more fully in U.S. Pat. No. 3,890,632 entitled STABILIZED SEMICONDUCTOR DEVICES AND METHOD OF MAKING SAME, which issued to W. E. Ham et al. on June 17, 1975; U.S. Pat. No. 4,178,191 entitled PROCESS OF MAKING A PLANAR MOS SILICON-ON-INSULATING SUBSTRATE DEVICE, which issued to D. W. Flatley on Dec. 11, 1979; U.S. Pat. No. 4,070,211 entitled TECHNIQUE FOR THRESHOLD CONTROL OVER EDGES OF DEVICES ON SILICON-ON-SAPPHIRE, which issued to E. Harari on Jan. 24, 1978; and co-pending U.S. patent application No. 093,011 entitled LOW LEAKAGE N-CHANNEL SOS TRANSISTORS AND METHOD OF MAKING THEM OF J. J. Fabula which issued on Feb. 24, 1981 as U.S. Pat. No. 4,252,574. Each of the aforementioned patents and patent application is incorporated herein by reference.